View ADM4857_256031.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

5 V Slew-Rate Limited Half- and Full-Duplex RS-485/RS-422 Transceivers ADM4850-ADM4857
FEATURES
EIA RS-485-/RS-422-compliant Data rate options ADM4850/ADM4854--115 kbps ADM4851/ADM4855--500 kbps ADM4852/ADM4856--2.5 Mbps ADM4853/ADM4857--10 Mbps Half- and full-duplex options Reduced slew rates for low EMI True fail-safe receiver inputs 5 A (maximum) supply current in shutdown mode Up to 256 transceivers on one bus Outputs high-z when disabled or powered off -7 V to +12 V bus common-mode range Thermal shutdown and short-circuit protection Pin-compatible with MAX308x Specified over the -40C to +85C temperature range Available in 8-lead SOIC and LFCSP packages
FUNCTIONAL BLOCK DIAGRAM
VCC VCC
ADM4850/ADM4851/ ADM4852/ADM4853
RO RE DE DI D R A B DI RO
ADM4854/ADM4855/ ADM4856/ADM4857
A R B Z D Y
04931-001
GND
GND
Figure 1.
APPLICATIONS
Low power RS-485 applications EMI-sensitive systems DTE-DCE interfaces Industrial control Packet switching Local area networks Level translators
GENERAL DESCRIPTION
The ADM4850-ADM4857 are differential line transceivers suitable for high speed half- and full-duplex data communication on multipoint bus transmission lines. They are designed for balanced data transmission and comply with EIA Standards RS-485 and RS-422. The ADM4850-ADM4853 are half-duplex transceivers, which share differential lines and have separate enable inputs for the driver and receiver. The full-duplex ADM4854-ADM4857 transceivers have dedicated differential line driver outputs and receiver inputs. The parts have a 1/8-unit-load receiver input impedance, which allows up to 256 transceivers on one bus. Since only one driver should be enabled at any time, the output of a disabled or powered-down driver is three-stated to avoid overloading the bus. The receiver inputs have a true fail-safe feature, which ensures a logic high output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before communication begins and when communication ends.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
The driver outputs are slew-rate limited to reduce EMI and data errors caused by reflections from improperly terminated buses. Excessive power dissipation caused by bus contention or by output shorting is prevented with a thermal shutdown circuit. The parts are fully specified over the commercial and industrial temperature ranges, and are available in 8-lead SOIC and LFCSP packages. Table 1. Selection Table
Part No ADM4850 ADM4851 ADM4852 ADM4853 ADM4854 ADM4855 ADM4856 ADM4857 Half-/Full-Duplex Half Half Half Half Full Full Full Full Data Rate 115 kbps 500 kbps 2.5 Mbps 10 Mbps 115 kbp 500 kbps 2.5 Mbps 10 Mbps
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADM4850-ADM4857 TABLE OF CONTENTS
Specifications..................................................................................... 3 ADM4850/ADM4854 Timing Specifications........................... 4 ADM4851/ADM4855 Timing Specifications........................... 4 ADM4852/ADM4856 Timing Specifications........................... 5 ADM4853/ADM4857 Timing Specifications........................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Test Circuits....................................................................................... 8 Switching Characteristics ................................................................ 9 Typical Performance Characteristics ........................................... 10 Circuit Description......................................................................... 12 Slew-Rate Control ...................................................................... 12 Receiver Input Filtering............................................................. 12 Half-/Full-Duplex Operation ................................................... 12 High Receiver Input Impedance .............................................. 13 Three-State Bus Connection..................................................... 13 Shutdown Mode ......................................................................... 13 Fail-Safe Operation .................................................................... 13 Current Limit and Thermal Shutdown ................................... 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 15
REVISION HISTORY
10/04--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADM4850-ADM4857 SPECIFICATIONS
V = 5 V 5%, TA = TMIN to TMAX, unless otherwise noted. Table 2.
Parameter DRIVER Differential Output Voltage, VOD Min Typ Max VCC 5 5 5 0.2 3 0.2 +200 +200 1.4 1.4 220 -200 96 -125 20 150 -30 0.8 1 Unit V V V V V V V mA mA V V A k mV mV k mA mA A V V mA A A A A A A A A A A A A A -7 V < VM < +12 V -7 V < VM < +12 V -7 V < VM < +12 V VIN = +12 V VIN = -7 V IOUT = +4 mA IOUT = -4 mA VOUT = GND or VCC 0.4 V VOUT 2.4 V DE = 0 V, RE = VCC (shutdown) DE = 0 V, RE = 0 V DE = VCC DE = 0 V, RE = VCC (shutdown) DE = 0 V, RE = 0 V DE = VCC DE = 0 V, RE = VCC (shutdown) DE = 0 V, RE = 0 V DE = VCC DE = 0 V, RE = VCC (shutdown) DE = 0 V, RE = 0 V DE = VCC Test Conditions/Comments R = , Figure 41 R = 50 (RS-422), Figure 4 R = 27 (RS-485), Figure 4 VTST = -7 V to 12 V, Figure 5 R = 27 or 50 , Figure 4 R = 27 or 50 , Figure 4 R = 27 or 50 , Figure 4 -7 V < VOUT < +12 V -7 V < VOUT < +12 V
2.0 1.5 1.5 |VOD| for Complementary Output States Common-Mode Output Voltage, VO |VO | for Complementary Output States Output Short-Circuit Current, VOUT = High Output Short-Circuit Current, VOUT = Low DRIVER INPUT LOGIC CMOS Input Logic Threshold Low CMOS Input Logic Threshold High CMOS Logic Input Current (DI) DE Input Resistance to GND RECEIVER Differential Input Threshold Voltage, VTH Input Hysteresis Input Resistance (A, B) Input Current (A, B) CMOS Logic Input Current (RE) CMOS Output Voltage Low CMOS Output Voltage High Output Short Circuit Current Three-State Output Leakage Current POWER SUPPLY CURRENT I (115 kbps Options)
-200 -200
2.0
0.125 -0.1 1 0.4 4.0 7 85 2 5 60 160 5 120 200 5 400 500 5 400 500
36 100 I (500 kbps Options) 80 120 I (2.5 Mbps Options) 250 320 I (10 Mbps Options) 250 320
1
Guaranteed by design.
Rev. 0 | Page 3 of 16
ADM4850-ADM4857
ADM4850/ADM4854 TIMING SPECIFICATIONS
V = 5 V 5%, TA = TMIN to TMAX, unless otherwise noted. Table 3.
Parameter DRIVER Maximum Data Rate Propagation Delay tPLH, tPHL Skew tSKEW Rise/Fall Time tR, tF Enable Time Disable Time Enable Time from Shutdown RECEIVER Propagation Delay tPLH, tPH Differential Skew tSKEW Enable Time Disable Time Enable Time from Shutdown Time to Shut Down Min 115 600 600 Typ Max Unit kbps ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions/Comments
2500 70 2400 2000 2000 4000
RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RL = 500 , CL = 100 pF, Figure 7, ADM4850 RL = 500 , CL = 15 pF, Figure 7, ADM4850 RL = 500 , CL = 100 pF, Figure 7, ADM4850 CL = 15 pF, Figure 8 CL = 15 pF, Figure 8 RL = 1 k, CL = 15 pF, Figure 9, ADM4850 RL = 1 k, CL = 15 pF, Figure 9, ADM4850 RL = 1 k, CL = 15 pF, Figure 9, ADM4850 ADM48501
400 5 20 4000 330
1000 255 50 50 3000
50
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4851/ADM4855 TIMING SPECIFICATIONS
V = 5 V 5%, TA = TMIN to TMAX, unless otherwise noted. Table 4.
Parameter DRIVER Maximum Data Rate Propagation Delay tPLH, tPHL Skew tSKEW Rise/Fall Time tR, tF Enable Time Disable Time Enable Time from Shutdown RECEIVER Propagation Delay tPLH, tPHL Differential Skew tSKEW Enable Time Disable Time Enable Time from Shutdown Time to Shut Down Min 500 250 200 Typ Max Unit kbps ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions/Comments
600 40 600 1000 1000 4000
RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RL = 500 , CL = 100 pF, Figure 7, ADM4851 RL = 500 , CL = 15 pF, Figure 7, ADM4851 RL = 500 , CL = 100 pF, Figure 7, ADM4851 CL = 15 pF, Figure 8 CL = 15 pF, Figure 8 RL = 1 k, CL = 15 pF, Figure 9, ADM4851 RL =1 k, CL = 15 pF, Figure 9, ADM4851 RL =1 k, CL = 15 pF, Figure 9, ADM4851 ADM48511
400 5 20 4000 330
1000 250 50 50 3000
50
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
Rev. 0 | Page 4 of 16
ADM4850-ADM4857
ADM4852/ADM4856 TIMING SPECIFICATIONS
V = 5 V 5%, TA = TMIN to TMAX, unless otherwise noted. Table 5.
Parameter DRIVER Maximum Data Rate Propagation Delay tPLH, tPHL Skew tSKEW Rise/Fall Time tR, tF Enable Time Disable Time Enable Time from Shutdown RECEIVER Propagation Delay tPLH, tPHL Differential Skew tSKEW Enable Time Disable Time Enable Time from Shutdown Time to Shut Down Min 2.5 50 Typ Max Unit Mbps ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions/Comments
180 50 140 180 180 4000
RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RL = 500 , CL = 100 pF, Figure 7, ADM4852 RL = 500 , CL = 15 pF, Figure 7, ADM4852 RL =500 , CL = 100 pF, Figure 7, ADM4852 CL = 15 pF, Figure 8 CL = 15 pF, Figure 8 RL = 1 k, CL = 15 pF, Figure 9, ADM4852 RL = 1 k, CL = 15 pF, Figure 9, ADM4852 RL = 1 k, CL = 15 pF, Figure 9, ADM4852 ADM48521
55 5 20 4000 330
190 50 50 50 3000
50
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4853/ADM4857 TIMING SPECIFICATIONS
V = 5 V 5%, TA = TMIN to TMAX, unless otherwise noted. Table 6.
Parameter DRIVER Maximum Data Rate Propagation Delay tPLH, tPHL Skew tSKEW Rise/Fall Time tR, tF Enable Time Disable Time Enable Time from Shutdown RECEIVER Propagation Delay tPLH, tPHL Differential Skew tSKEW Enable Time Disable Time Enable Time from Shutdown Time to Shut Down Min 10 0 Typ Max Unit Mbps ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions/Comments
30 10 30 35 35 4000
RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RLDIFF = 54 , CL1 = CL2 = 100 pF, Figure 6 RL = 500 , CL = 100 pF, Figure 7, ADM4853 RL = 500 , CL = 15 pF, Figure 7, ADM4853 RL = 500 , CL = 100 pF, Figure 7, ADM4853 CL = 15 pF, Figure 8 CL = 15 pF, Figure 8 RL = 1 k, CL = 15 pF, Figure 9, ADM4853 RL = 1 k, CL = 15 pF, Figure 9, ADM4853 RL = 1 k, CL = 15 pF, Figure 9, ADM4853 ADM48531
55 5 20 4000 330
190 30 50 50 3000
50
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
Rev. 0 | Page 5 of 16
ADM4850-ADM4857 ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter VCC to GND Digital I/O Voltage (DE, RE, DI, ROUT) Driver Output/Receiver Input Voltage Operating Temperature Range Storage Temperature Range JA Thermal Impedance SOIC LFCSP Lead Temperature Soldering (10 s) Vapour Phase (60 s) Infrared (15 s) Rating 6V -0.3 V to VCC + 0.3 V -9 V to +14 V -40C to +85C -65C to +125C 110C/W 62C/W 300C 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 16
ADM4850-ADM4857 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
RO 1 RE 2 DE 3
Figure 2. ADM4850-ADM4853 Pin Configuration
Table 8. ADM4850-ADM4853 Pin Descriptions
Pin No. 1 2 Mnemonic RO RE Description Receiver Output. When enabled, if (A-B) -30 mV, then RO = high. If (A-B) -200 mV, then RO = low. Receiver Output Enable. A low level enables the receiver output, RO. A high level places it in a high impedance state. Driver Output Enable. A high level enables the driver differential inputs A and B. A low level places it in a high impedance state. Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, while a logic high on DI forces A high and B low. Ground. Noninverting Receiver Input A/Driver Output A. Inverting Receiver Input B/Driver Output B. 5 V Power Supply.
3 4 5 6 7 8
DE DI GND A B VCC
VCC 1 RO 2 DI 3
Figure 3. ADM4854-ADM4857 Pin Configuration
Table 9. ADM4854-ADM4857 Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic VCC RO DI GND Y Z B A Description 5 V Power Supply. Receiver Output. When enabled, if (A-B) -30 mV, then RO = high. If (A-B) -200 mV, then RO = low. Driver Input. When the driver is enabled, a logic low on DI forces Y low and Z high, while a logic high on DI forces Y high and Z low. Ground. Driver Noninverting Output. Driver Inverting Output. Receiver Inverting Input. Receiver Noninverting Input.
Rev. 0 | Page 7 of 16
04931-003
Z TOP VIEW GND 4 (Not to Scale) 5 Y
6
ADM4854/ ADM4855/ ADM4856/ ADM4857
8 7
A B
04931-002
A TOP VIEW DI 4 (Not to Scale) 5 GND
6
ADM4850/ ADM4851/ ADM4852/ ADM4853
8 7
VCC B
ADM4850-ADM4857 TEST CIRCUITS
VCC
R VOD
04931-004
A 0V OR 3V DE S1 B CL
RL VOUT
S2
04931-007
R
VOC
DE IN
Figure 4. Driver Voltage Measurement
Figure 7. Driver Enable/Disable
375
A
04931-005
04931-008
VOD3
60
VTST
B
RE
VOUT CL
375
Figure 5. Driver Voltage Measurement over Common-Mode Voltage Range
Figure 8. Receiver Propagation Delay
+1.5V VCC S1
A RLDIFF B
CL1
04931-006
-1.5V RE CL RE IN
RL VOUT
S2
04931-009
CL2
Figure 6. Driver Propagation Delay
Figure 9. Receiver Enable/Disable
Rev. 0 | Page 8 of 16
ADM4850-ADM4857 SWITCHING CHARACTERISTICS
3V 1.5V 0V B VO A 1.5V
3V DE 1.5V 1.5V 0V
tPLH
1/2VO
tPHL
tZL
2.3V
tLZ
A, B
VOL +0.5V VOL
tSKEW = |tPLH -tPHL|
5V 90% POINT 10% POINT 90% POINT
tZH
A, B 2.3V
tHZ
VOH
04931-012 04931-013
VOH -0.5V 0V
0V
10% POINT
tR
tF
04931-010
Figure 12. Driver Enable/Disable Timing Figure 10. Driver Propagation Delay, Rise/Fall Timing
3V RE 1.5V 1.5V 0V
A, B 0V 0V
tZL
1.5V O/P LOW
VOH
tLZ
tPLH
R
tPHL
tZH
R
04931-011
VOL +0.5V VOL
O/P HIGH 1.5V
tHZ
VOH VOH -0.5V
RO
1.5V
tSKEW = |tPLH -tPHL|
1.5V VOL
0V
Figure 11. Receiver Propagation Delay
Figure 13. Receiver Enable/Disable Timing
Rev. 0 | Page 9 of 16
ADM4850-ADM4857 TYPICAL PERFORMANCE CHARACTERISTICS
400 ADM4853: DE = VCC 350
0.40
UNLOADED SUPPLY CURRENT (A)
0.35
300 ADM4853: DE = GND 250 200 ADM4850: DE = VCC 150 100 ADM4850: DE = GND
04931-014
OUTPUT LOW VOLTAGE (V)
0.30
0.25
0.20
04931-017
50 0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125
0.15 -50
-25
0
25 50 TEMPERATURE (C)
75
100
125
Figure 14. Unloaded Supply Current vs. Temperature
Figure 17. Receiver Output Low Voltage vs. Temperature
50 45
RECEIVER OUTPUT CURRENT (mA)
4.6
40 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 RECEIVER OUTPUT LOW VOLTAGE (V) 1.8 2.0
04931-015
4.5
OUTPUT HIGH VOLTAGE (V)
4.4
4.3
4.2
4.1
04931-018
4.0 -50
-25
0
25 50 TEMPERATURE (C)
75
100
125
Figure 15. Output Current vs. Receiver Output Low Voltage
Figure 18. Receiver Output High Voltage Temperature
90
RECEIVER OUTPUT CURRENT (mA)
5
DRIVER OUTPUT CURRENT (mA)
80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 DIFFERENTIAL OUTPUT VOLTAGE (V) 4.5
04931-019
0
-5
-10
-15
04931-016
-20 3.5
4.0 4.5 5.0 RECEIVER OUTPUT HIGH VOLTAGE (V)
5.5
5.0
Figure 16. Output Current vs. Receiver Output High Voltage
Figure 19. Driver Output Current vs. Differential Output Voltage
Rev. 0 | Page 10 of 16
ADM4850-ADM4857
120
800 700
100
PROPAGATION DELAY (ns)
OUTPUT CURRENT (mA)
ADM4855 600 500 400 300 200 ADM4853
04931-020 04931-023
80
60
40
20
100 0 -50 -25
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) 4.0 4.5
5.0
0
25 50 75 TEMPERATURE (C)
100
125
Figure 20. Output Current vs. Driver Low Voltage
Figure 23. Receiver Propagation Delay vs. Temperature
-10
OUTPUT CURRENT (mA)
-30
3
-50
-70
-110 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT VOLTAGE (V) 4.0 4.5 5.0
04931-021
4
CH1 1.00VBW CH3 2.00VBW
CH2 1.00VBW CH4 5.00V
M 400ns
CH3
2.00V
Figure 21. Output Current vs. Driver Output High Voltage
Figure 24. Driver/Receiver Propagation Delay (ADM4855, 500 kbps)
450 400
PROPAGATION DELAY (ns)
350 ADM4855 300 250 200 150 100 50 0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 ADM4853
04931-022
1
2 4
04931-025
CH1 2.00VBW CH3 1.00VBW
CH2 1.00V CH4 5.00V
M 50.0ns
CH1
480mV
Figure 22. Driver Propagation Delay vs. Temperature
Figure 25. Driver/ Receiver Propagation Delay (ADM4855, 4 Mbps)
Rev. 0 | Page 11 of 16
04931-024
-90
2
ADM4850-ADM4857 CIRCUIT DESCRIPTION
The ADM4850-ADM4857 are high speed RS-485/RS-422 transceivers offering enhanced performance over industrystandard devices. All devices in the family contain one driver and one receiver, but offer a choice of performance options. The devices feature true fail-safe operation, which means that a logic high receiver output is guaranteed when the receiver inputs are open-circuit or short-circuit, or when they are connected to a terminated transmission line with all drivers disabled (see the Fail-Safe Operation section).
RECEIVER INPUT FILTERING
The receivers of all the devices incorporate input hysteresis. In addition, the receivers of the 115 kbps ADM4850/ADM485 and the 500 kbps ADM4851/ADM4855 incorporate input filtering. This enhances noise immunity with differential signals that have very slow rise and fall times. However, it causes the propagation delay to increase by 20%.
HALF-/FULL-DUPLEX OPERATION
Half-duplex operation implies that the transceiver can transmit and receive, but it can only do one of these at any given time. However, with full-duplex operation, the transceiver can transmit and receive simultaneously. The ADM4850-ADM4853 are half-duplex devices in which the driver and receiver share differential bus terminals. The ADM4854-ADM4857 are fullduplex devices, which have dedicated driver output and receiver input pins. Figure 26 and Figure 27 show typical half- and fullduplex topologies.
SLEW-RATE CONTROL
The ADM4850/ADM4854 feature a controlled slew-rate driver that minimizes electromagnetic interference (EMI) and reduces reflections caused by incorrectly terminated cables, allowing error-free data transmission rates up to 115 kbps. The ADM4851/ ADM4855 offer a higher limit on driver output slew rate, allowing data transmission rates up to 500 kbps. The driver slew rates of the ADM4852/ADM4856 and the ADM4853/ADM4857 are not limited, offering data transmission rates up to 2.5 Mbps and 10 Mbps, respectively.
ADM4850/ADM4851/ ADM4852/ADM4853
RO RE DE DI D B A B A B B R A A
ADM4850/ADM4851/ ADM4852/ADM4853
R RO RE DE D DI
ADM4850/ADM4851/ ADM4852/ADM4853
ADM4850/ADM4851/ ADM4852/ADM4853
R D
R D
MAXIMUM NUMBER OF TRANSCEIVERS ON BUS: 256
Figure 26. Typical Half-Duplex RS-485 Network Topology
VDD VDD
ADM4854/ADM4855/ ADM4856/ADM4857
RO R
A
Z
ADM4854/ADM4855/ ADM4856/ADM4857
D DI
B Z DI D Y GND
Y A R B GND RO
04931-027
Figure 27. Typical Full-Duplex Point-to-Point RS-485 Network Topology
Rev. 0 | Page 12 of 16
04931-026
RO RE DE
DI
RO RE DE
DI
ADM4850-ADM4857
HIGH RECEIVER INPUT IMPEDANCE
The input impedance of the ADM485x receivers is 96 k, which is 8 times higher than the standard RS-485 unit load of 12 k. This 96 k impedance, enables a standard driver to drive 32 unit loads or be connected to 256 ADM485x receivers. An RS-485 bus, driven by a single standard driver, can be connected to a combination of ADM485x and standard unit load receivers, up to an equivalent of 32 standard unit loads.
FAIL-SAFE OPERATION
The ADM4850-ADM4857 offer true fail-safe operation while remaining fully compliant with the 200 mV EIA/TIA-485 standard. A logic-high receiver output is generated when the receiver inputs are shorted together or open-circuit, or when they are connected to a terminated transmission line with all drivers disabled. This is done by setting the receiver threshold between -30 mV and -200 mV. If the differential receiver input voltage (A-B) is greater than or equal to -30 mV, RO is logic high. If A-B is less than or equal to -200 mV, RO is logic low. In the case of a terminated bus with all transmitters disabled, the receiver's differential input voltage is pulled to 0 V by the ADM485x's internal circuitry, which results in a logic high with 30 mV minimum noise margin.
THREE-STATE BUS CONNECTION
The half-duplex parts have a driver enable (DE) pin that enables the driver outputs when taken high, or puts the driver outputs into a high impedance state when taken low. Similarly, the halfduplex devices have an active-low receiver enable (RE) pin. Taking this pin low enables the receiver, while taking it high puts the receiver outputs into a high impedance state. This allows several driver outputs to be connected to an RS-485 bus. Note that only one driver should be enabled at a time, while many receivers can be enabled.
CURRENT LIMIT AND THERMAL SHUTDOWN
The ADM485x incorporates two protection mechanisms to guard the drivers against short circuits, bus contention, or other fault conditions. The first is a current-limiting output stage, which protects the driver against short circuits over the entire common-mode voltage range by limiting the output current to approximately 70 mA. Under extreme fault conditions where the current limit is not effective, a thermal shutdown circuit puts the driver outputs into a high impedance state if the die temperature exceeds 150C, and does not turn them back on until the temperature falls to 130C.
SHUTDOWN MODE
The ADM4850-ADM4853 have a low power shutdown mode, which is enabled by taking RE high and DE low. If shutdown mode is not used, the fact that DE is active high and RE is active low offers a convenient way of switching the device between transmit and receive by tying DE and RE together. The devices are guaranteed not to enter shutdown mode if DE and RE are driven in this way. If DE is low and RE is high for less than 50 ns, the device does not enter shutdown mode. If DE is low and RE is high for less than 3000 ns, the device is guaranteed to enter shutdown mode.
Rev. 0 | Page 13 of 16
ADM4850-ADM4857 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5 4
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440) 5.80 (0.2284)
3.00 BSC SQ 0.45
0.60 MAX
0.50 0.40 0.30
PIN 1 INDICATOR
8
1
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
PIN 1 INDICATOR
TOP VIEW
2.75 BSC SQ 0.50 BSC
5
(BOTTOM VIEW)
EXPOSED PAD
1.50 REF
4
1.90 1.75 1.60
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
0.90 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
0.25 MIN
1.60 1.45 1.30
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
SEATING PLANE
Figure 28. 8-Lead Standard Small Outline Package [SOIC] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
Figure 29. 8-Lead Lead Frame Chip Scale Package [LFCSP] (CP-8-2) Dimensions shown in millimeters
Rev. 0 | Page 14 of 16
ADM4850-ADM4857
ORDERING GUIDE
Model ADM4850ACP-REEL ADM4850ACP-REEL7 ADM4850AR ADM4850AR-REEL ADM4850AR-REEL7 ADM4851ACP-REEL ADM4851ACP-REEL7 ADM4851AR ADM4851AR-REEL ADM4851AR-REEL7 ADM4852ACP-REEL ADM4852ACP-REEL7 ADM4852AR ADM4852AR-REEL ADM4852AR-REEL7 ADM4853ACP-REEL ADM4853ACP-REEL7 ADM4853AR ADM4853AR-REEL ADM4853AR-REEL7 ADM4854AR ADM4855AR ADM4855AR-REEL ADM4855AR-REEL7 ADM4856AR ADM4856AR-REEL ADM4856AR-REEL7 ADM4857AR ADM4857AR-REEL ADM4857AR-REEL7 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead Lead Frame Chip Scale Package 8-Lead Lead Frame Chip Scale Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Lead Frame Chip Scale Package 8-Lead Lead Frame Chip Scale Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Lead Frame Chip Scale Package 8-Lead Lead Frame Chip Scale Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Lead Frame Chip Scale Package 8-Lead Lead Frame Chip Scale Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package 8-Lead Standard Small Outline Package Package Type CP-8-2 CP-8-2 R-8 R-8 R-8 CP-8-2 CP-8-2 R-8 R-8 R-8 CP-8-2 CP-8-2 R-8 R-8 R-8 CP-8-2 CP-8-2 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 Branding M0R M0R
M0S M0S
M0T M0T
M0U M0U
Rev. 0 | Page 15 of 16
ADM4850-ADM4857 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04931-0-10/04(0)
Rev. 0 | Page 16 of 16

▲Up To Search▲

Price & Availability of ADM4857

	To Download ADM4857 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .